2001 Silicon Nanoelectronics Workshop

June 10-11, 2001
Rihga Royal Hotel Kyoto, Kyoto, Japan

Highlights of the Workshop

Invited Speakers

R. Chau, Intel, USA,
"30nm and 20nm Physical Gate Length CMOS Transistors"
H.-S. P. Wong, IBM, USA,
"Devices and Technologies for Sub-25 nm CMOS"
K. Yano, Hitachi, Japan,
"Nano-Structured Memories: From Technology Innovation to Value Innovation"
Y. Ono, NTT, Japan,
"Arithmetic Operation by Single-Electron Transistors"
N. Sano, K. Matsuzawa, A. Hiroki, and N. Nakayama, Tsukuba University, Japan,
"Discrete Random Dopants and Vth Fluctuations in Sub-100 nm MOSFETs"
W. Porod, University of Notre Dame, USA,
"Towards nanoelectronic circuits: CMOS, SET's, and QCA's"

Panel Discussion

Subject:Prospects of Novel CMOS Device Structures
Moderator:H. Kawaura (NEC)
H. Shin (KAIST)
Panelist:R. Chau (Intel)
H.-S. P. Wong (IBM)
D. Hisamoto (Hitachi)
T. Skotnicki (STMicroelectronics)


2001 Silicon Nanoelectronics Workshop

June 10-11, 2001
Rihga Royal Hotel Kyoto, Kyoto, Japan

(held prior to VLSI Technology Symposium, Satellite Workshop of VLSI Symposia) Sponsored by the Japan Society of Applied Physics and the IEEE Electron Device Society

General Information

The 2001 Silicon Nanoelectronics Workshop will be held at Rihga Royal Hotel Kyoto, Japan on June 10-11, 2001, just prior to VLSI Symposium on Technology as a Satellite Workshop of the VLSI Symposia. The workshop will focus on silicon-related nanoelectronics to bridge a gap between the Si nano-technology and the "real" VLSI world. The first Silicon Nanoelectronics Workshop was successfully held in June, 1996 at Honolulu, Hawaii, USA. The 2001 Silicon Nanoelectronics Workshop will be the sixth in a series of annual workshops.

  1. Call for Paper
  2. Call for Late News Paper
  3. Program
  4. Registration Information
  5. Committee

hiramoto@nano.iis.u-tokyo.ac.jp
Last modified: Fri Jun 8 21:43:00 JST 2001