Research Subjects in Hiramoto Lab.

1. Device Improvement by Cooperation with Circuits
   1. Ultra-Low Power MOSFET Operating at 0.5 V

      Extremely low voltage and low power operation is essential for VLSI circuits and devices. In this study, we aim at the 0.5 V operation and investigate the new scheme for obtaining the high speed and ultra-low power simultaneously by the cooperation of device and circuit. When the device is scaled and the supply voltage is reduced, it will become very hard to suppress the stand-by leakage power by device itself. Therefore, the device/circuit cooperation will be essential. We have proposed a new circuit/device cooperative scheme, BGMOS (Boosted Gate MOS) [1], where a MOS switch is connected in series with the main CMOS circuit. The switch MOS has thicker gate dielectric thickness, higher threshold voltage, and higher gate voltage than Vdd. Since VTCMOS, described in the next section, will be not able to suppress the stand-by leakage in the future [2], the combination of BGMOS and VTCMOS will be indispensable in the future low power VLSI.

      [1]	T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto, T. Sakurai, "Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration", Custom Integrated Circuits Conference, Florida, USA, pp. 409 - 412, May, 2000.
      [2]	T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 4B, pp. 2854 - 2858, April, 2001.

   2. Variable Threshold Voltage CMOS (VTCMOS)

      We investigate the device design of variable threshold voltage CMOS (VTCMOS) where the threshold voltage at the active mode and stand-by mode is controlled by well potential [1]. VTCMOS is the one of the most promising device/circuit cooperative schemes. The VTCMOS scheme is very effective for the stand-by leakage suppression when the supply voltage is above 1.5 V. However, it has been found that, the low power VTCMOS scheme has no scalability and the subthreshold leak can not be suppressed in the future when the supply voltage is scaled down [2]. On the other hand, when VTCMOS act as a high-speed scheme at low supply voltage, its advantage is scalable [2]. We also examined the origin of the critical substrate bias in VTCMOS. When the substrate bias is larger than the critical voltage, a device with larger body effect has higher current drive. This sharply contradicts with the conventional device design guideline, and a new device guideline is proposed for VTCMOS [3]. Although the body effect should usually be small in series connected circuits such as NAND, it has been newly found that the body effect factor should be large in VTCMOS even in the series connected circuits [4]. The origin of this phenomenon is the relaxation of the velocity saturation effect [4].

      [1]	H. Koura, M. Takamiya, and T. Hiramoto, "Optimum Conditions of Body Effect Factor and Substrate Bias in Variable Threshold Voltage MOSFETs" Japanese Journal of Applied Physics, Vol. 39, No. 4B, pp. 2312 - 2317, April, 2000.
      [2]	T. Hiramoto, M. Takamiya, H. Koura, T. Inukai, H. Gomyo, H. Kawaguchi, and T. Sakurai, "Optimum Device Parameters and Scalability of Variable Threshold Voltage Complementary MOS (VTCMOS)", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 4B, pp. 2854 - 2858, April, 2001.
      [3]	T. Inukai, H. Im, and T. Hiramoto, "Origin of Critical Substrate Bias in Variable Threshold Voltage Complementary MOS (VTCMOS)", Japanese Journal of Applied Physics, Vol. 41, Part 1, No. 4B, pp. 2312 - 2315, April, 2002.
      [4]	T. Inukai, T. Hiramoto, and T. Sakurai, "Variable Threshold Voltage CMOS (VTCMOS) in Series Connected Circuits", 2001 International Symposium on Low Power Electronics and Design, Hilton Waterfront Beach Resort, Huntington Beach, CA, USA, pp. 201 - 206, August, 2001.

2. Device Scaling and Device Physics
   1. SOI MOSFET

      We are studying the device physics and short channel effects in Silicon-on-Insulator (SOI) MOSFETs which have attracted much attention as a low power device. We are invited to International Conference such as IEEE SOI Conference and SSDM to give a talk on SOI research [1,2]. We have proposed a new MOSFET structure with triangular wire channel array on SOI for a possible nano-scale MOSFET, and have fabricated [3]. In this structure, the gate electrode covers only two upper sides of the triangle channels, and the fabrication process is much easier than that of double gate devices. It is demonstrated that the short channel effects are much more suppressed than fully depleted single gate SOI devices. We also discuss the mechanisms of the dynamic pass gate leakage problem in partially depleted SOI devices [4] and the enhancement of statistical impurity fluctuations in fully depleted SOI devices.

      [1]	T. Hiramoto (Invited), "Nano-Scale Silicon MOSFET: Towards Non-Traditional and Quantum Devices", 2001 IEEE International SOI Conference, Sheraton Tamarron Resort, Durango, CO, USA, pp. 8 - 10, October, 2001.
      [2]	T. Hiramoto (Invited), "Future Electron Devices and SOI Technology", 2002 International Conference on Solid State Devices and Materials (SSDM), Nagoya Congress Center, September, 2002.
      [3]	T. Saito, T. Saraya, T. Inukai, H. Majima, T. Nagumo, and T. Hiramoto, "Suppression of Short Channel Effect in Triangular Parallel Wire Channel MOSFETs", IEICE Transactions on Electronics, Vol. E85-C, No. 5, pp. 1073 - 1078, May, 2002.
      [4]	T. Saraya and T. Hiramoto, "Mechanisms of dynamic pass leakage current in partially depleted SOI MOSFETs", 1999 IEEE International SOI Conference, Doubletree Hotel Sonoma County, CA, USA, pp. 84 - 85, October, 1999.

   2. Quantum Mechanical Effects in Very Narrow MOSFETs

      It is well known that the threshold voltage increases in very thin SOI MOSFETs by quantum confinement effects. It is expected that in nano-scale ultra-narrow channel MOSFET, the carriers are confined not only vertically but also horizontally and that a stronger quantum confinement is attained. In this study, we have demonstrated for the first time by experiments and simulation this effect [1,2] and proposed a new device design for performance improvement using this effect [3]. We named this phenomenon the quantum mechanical narrow channel effect. The fabrication process has been improved and extremely narrow channel MOSFETs have been fabricated. The threshold voltage increase due to the quantum confinement has been clearly is observed when the width is less than 10 nm [1,2]. We have also successfully fabricated ultra-narrow channel MOSFET with n-type and p-type source/drain [3]. In this device, quantum confinements of both electrons and holes can be measured in the same channel. It is found that the quantum mechanical narrow channel effect takes place also in p-type narrow channel MOSFETs [3]. We have proposed a new threshold voltage adjustment method using the quantum mechanical effect. We also discussed the carrier mobility in narrow channel MOSFETs and found that <100>-oriented narrow channel MOSFETs have higher mobility than <110>-oriented channel MOSFETs [3]. These results were presented in International Electron Devices Meeting (IEDM) in 1999 and 2001 [1,3].

      [1]	H. Majima, H. Ishikuro, and T. Hiramoto, "Threshold Voltage Increase by Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs", 1999 IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 379 - 382, December, 1999.
      [2]	H. Majima, H. Ishikuro, and T. Hiramoto, "Experimental Evidence for Quantum Mechanical Narrow Channel Effect in Ultra-Narrow MOSFETs", IEEE Electron Device Letters, Vol. 21, No. 8, pp. 396 - 398, August, 2000.
      [3]	H. Majima, Y. Saito, and T. Hiramoto, "Impact of Quantum Mechanical Effects on Design of Nano-Scale Narrow Channel n- and p-type MOSFETs", 2001 International Electron Devices Meeting (IEDM), Washington D.C., December, pp. 733 - 736, 2001.

3. New Function by Using New Physics and Concept
   1. Physics of Silicon Single Electron Devices

      Fabrication and physics of silicon single electron devices have been extensively studied for the future ultra-low power VLSI device applications [1]. We adopt silicon as a material to consider the compatibility with the VLSI process, and our research work is recognized as one of the pioneering works in this field. In a MOSFET with point-contact channel, a silicon dot is naturally formed, and the device acts as a single electron transistor even at room temperature [2]. So far, large Coulomb blockade oscillations whose peak/valley ratio is as high as 2 has been observed at room temperature [3]. The quantum mechanical effects in dots play an important role in transport, because the silicon dot size is less than 10 nm in room temperature operating devices. The negative differential conductance originating from the quantum effects have been observed [2,4]. We have developed a new process that suppresses the parasitic series resistance and clearer quantum effects have been observed. As a result, a staircase feature due to large quantum level spacing in the dot is observed in I-V characteristics [5]. The formation mechanisms of a quantum dot and tunneling barriers have been also studied [6].

      [1]	H. Ishikuro, T. Fujii, T. Saraya, G. Hashiguchi, T. Hiramoto, and T. Ikoma, "Coulomb Blockade Oscillations at Room Temperature in a Si Quantum Wire Metal-Oxide-Semiconductor Field-Effect-Transistor Fabricated by Anisotropic Etching on a Silicon-on-Insulator Substrate", Applied Physics Letters, Vol. 68, No. 25, pp. 3585 - 3587, June, 1996.
      [2]	H. Ishikuro and T. Hiramoto, "Quantum mechanical effects in the silicon quantum dot in a single-electron-transistor", Applied Physics Letters, Vol. 71, No. 25, pp. 3691 - 3693, December, 1997.
      [3]	M. Saitoh, N. Takahashi, H. Ishikuro, and T. Hiramoto, "Large Electron Addition Energy above 250 meV in the Silicon Quantum Dot in a Single Electron Transistor", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 3B, pp. 2010 - 2012, March, 2001.
      [4]	M. Saitoh, T. Saito, T. Inukai, and T. Hiramoto, "Transport spectroscopy of the ultrasmall silicon quantum dot in a single-electron transistor", Applied Physics Letters, Vol. 79, No. 13, pp. 2025 - 2027, September, 2001.
      [5]	M. Saitoh and T. Hiramoto, "Observation of current staircase due to large quantum level spacing in a silicon single-electron transistor with low parasitic series resistance", Journal of Applied Physics, Vol. 91, No. 10, pp. 6725 - 6728, May, 2002.
      [6]	H. Ishikuro and T. Hiramoto, "On the origin of tunneling barriers in silicon single electron and single hole transistors", Applied Physics Letter, Vol. 74, No. 8, pp. 1126 - 1128, February, 1999.

   2. Device Application of Silicon Quantum Dots

      MOSFETs with many silicon nano-dots in gate oxide have various characteristics, including memory effect, characteristics control and electron number control. We have fabricated the memory device using this structure and investigate the effect of interface traps on memory characteristics [1]. By combining the memory and above single electron transistor, we fabricate a new single electron transistor whose peak position can be controlled [2], and we also successfully integrated the single electron transistors [3]. We have also demonstrated that the distribution of device characteristics can be suppressed using the silicon dot, because the number of electrons in the dot is always an integer [4].

      [1]	Y. Shi, K. Saito, H. Ishikuro, and T. Hiramoto, "Effects of traps on charge storage characteristics in metal-oxide-semiconductor memory structures based on silicon nanocrystals", Journal of Applied Physics, Vol. 84, No. 4, pp. 2358 - 2360, August, 1998.
      [2]	N. Takahashi, H. Ishikuro, and T. Hiramoto, "Control of Coulomb blockade oscillations in silicon single electron transistor using silicon nano-crystal floating gates", Applied Physics Letters, Vol. 76, No. 2, pp. 209 - 211, January, 2000.
      [3]	N. Takahashi, H. Ishikuro, and T. Hiramoto, "A Directional Current Switch Using Silicon Single Electron Transistors Controlled by Charge Injection into Silicon Nano-Crystal Floating Dots", 1999 IEEE International Electron Devices Meeting (IEDM), Washington D.C., USA, pp. 371 - 374, December, 1999.
      [4]	H. N. Wang, N. Takahashi, H. Majima, T. Inukai, and T. Hiramoto, "Effects of Dot Size and its Distribution on Electron Number Control in Metal-Oxide-Semiconductor-Field-Effect-Transistor Memories Based on Silicon Nanocrystal Floating Dots", Japanese Journal of Applied Physics, Vol. 40, Part 1, No. 3B, pp. 2038 - 2040, March, 2001.